Verilog Simulations/Testing

Hello all,

Finally cracked out my Icebreaker and started playing with it, but quickly wanted to run simulations with an open source tool. Any suggestions? Long ago, I used Icarus and GTKWave, but figured there must be something newer/better.

Also, anyone using SystemVerilog with the Icebreaker? Any issues?

Thanks for the advice!

Jay

I think the only other simulator is Verilator, which is free and open source, but a bit different than icarus. It does use GTKWave for viewing the results though.

Related, I’m in the process of switching from Icarus to Verilator because Icarus does not support the SystemVerilog commands I have started to use (always_ff, always_comb) and Verilator does.

Yosys works fine with the limited SystemVerilog commands I have used so far, you do have to remember to use the -sv flag though.

Are you sure iverilog doesn’t support theses ? Are you using the latest ? And are you enabling SV with -g2012 ?

ah, well I was using -g2012 but I was on the latest stable branch and saw some chatter on forums about those commands not being supported. It looks like support for those commands was added to the dev branch in late 2019. I upgraded and now it sort of works, getting this error:

sorry: constant selects in always_* processes are not currently supported (all bits will be included)

from this code:

always_comb
begin
case(mode[1:0])
2’b11: input_sum_free = bias + voct + VCO_RANGE_OFFSET + transpose;
2’b10: input_sum_free = bias + voct + transpose;
2’b01: input_sum_free = bias + fm_cv + voct + VCO_RANGE_OFFSET + transpose;
2’b00: input_sum_free = bias + fm_cv + voct + transpose;
endcase
end

not to derail the thread, just saying it seems like systemverilog support in iverilog may be pretty fresh

Thanks. I ended up using iverilog and GTKWave. Easy enough to setup, after I remembered some of my Verilog-fu. Took longer than I want to admit.